This invention relates generally to programmable logic devices and specifically to multiplication functions in a field programmable gate array (FPGA).
A Field Programmable Gate Array (FPGA) is a general purpose device that can be programmed by an end user to perform one or more selected functions. An FPGA typically includes an array of individually configurable logic blocks (CLBs), each of which is programmably interconnected to other CLBs and to input/output (I/O) pins via a programmable routing structure to provide the selected function. U.S. Pat. No. 5,883,525, issued Mar. 16, 1999 to Tavana et al, and incorporated herein by reference, discloses an FPGA architecture having a plurality of repeatable cores tiles surrounded by I/O tiles. Each core tile has a CLB and a programmable routing matrix. The tiles are programmably interconnected to each other via their programmable routing matrices. U.S. Pat. No. 5,933,023, issued Aug. 3, 1999 to Young, and incorporated herein by reference, discloses an FPGA architecture having columns of blocks of random access memory (RAM) interposed between columns of core tiles to provide RAM functions to the FPGA. The RAM blocks each include a programmable routing matrix of the type in the core tiles, and may be accessed by the CLBs using dedicated connect lines rather than the general interconnect structure. U.S. Pat. No. 5,914,616 to Young et al describes an FPGA architecture in which logic blocks are connected to switch matrices through input and output multiplexers, and is incorporated herein by reference. Other suitable FPGA architectures are described in The Xilinx 1999 Data Book entitled xe2x80x9cThe Programmable Logic Data Bookxe2x80x9d, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.
As known in the art, each CLB of an FPGA is individually programmable to perform a variety of logic functions, such as addition. Many CLBs can be configured together to implement more complex logic functions, ranging from simple multipliers to more complex microprocessors. For example, U.S. Pat. No. 5,754,459, issued May 19, 1998 to Telikepalli, and incorporated by reference herein, teaches implementing a multiplier circuit using a number of CLBs in an FPGA architecture. However, implementing a multiplier using CLBs of an FPGA architecture may require a significant number of CLBs. For example, in the Virtex family of FPGAs available from Xilinx, Inc., implementing a 16xc3x9716 multiplier requires at least 60 CLBs. Implementing a multiplier in this manner not only consumes valuable CLB resources, but also consumes valuable general interconnect resources, which in turn may slow performance of the FPGA device.
One solution is to provide a dedicated multiplier within the FPGA to free valuable CLB resources for other functions. However, multipliers require a significant amount of input and output routing resources, which undesirably increases silicon area of the FPGA. Since it is often necessary to perform multiplication functions in an FPGA, it is would be desirable to implement a multiplier in an FPGA without consuming valuable CLB resources and without significantly increasing silicon area.
The present invention provides an alternative structure that shares routing resources with a programmable structure having variable width. When the programmable structure is being used only partly, the routing resources for the remaining portion of the programmable structure can be used by the alternative structure, and yet the alternative structure requires almost no additional silicon area for routing resources. In accordance with one embodiment of the present invention, one or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share I/O routing resources. In one embodiment, the multi-function tile includes a configurable, dual-ported RAM and a multiplier that share I/O resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBS) of the product are selectively provided onto the first output data bus, and the least significant bits (LSBS) of the product are selectively provided onto the second output data bus.
For this multiplier embodiment, in the configuration mode that uses the multiplier, the multiplier can be accessed simultaneously with reading and writing to the RAM or can be accessed without reading or writing to the RAM. During a write operation to the RAM, the RAM receives a number of LSBs from the first and second input data buses as input data, and the multiplier simultaneously receives a number of MSBs from the first and second input data buses as operands. During a read operation from the RAM, a first data word from the RAM and the MSBs of the product from the multiplier are concatenated onto the first output bus, and a second data word from the RAM and the LSBs of the product from the multiplier are concatenated onto the second output data bus. In this manner, RAM access and multiplication operations may be performed simultaneously.